The following relates to the light emission, lighting, illumination, and related arts. Example illustrated embodiments relate to mounting and packaging of light emitting diode chips. However, the following is amenable to other similar applications, such as mounting and packaging of vertical cavity surface emitting laser chips, organic light emitting chips, and so forth.
A light emitting diode chip typically includes a substrate on which a stack of semiconductor layers is deposited epitaxially or otherwise formed. The stack of semiconductor layers define a pn junction configured to emit light when suitably electrically energized. Typically, processing operations such as lithography, metallization, passivation, and so forth are applied to define electrodes for electrically energizing the chip. In a vertical chip design, electrodes are formed on opposite sides of the chip, that is, on the stack of semiconductor layers and on the substrate (or on the “backside” of the stack of semiconductor layers if the substrate is removed, for example by laser lift-off). In a lateral design, electrodes are formed only on the stack of semiconductor layers.
In the flip chip bonding technique, the chip is bonded in “flipped” fashion with the stack of semiconductor layers bonded to the sub-mount or other mounting surface, and the substrate arranged away from or distal from the sub-mount or other mounting surface. The generated light passes through the substrate, which should in such a design be light transmissive, and is emitted. In some embodiments, the substrate is removed after the flip chip bonding, for example by a laser lift-off process, in which case the substrate can be either light transmissive or opaque. For vertical designs in which the substrate is retained, the substrate should also be electrically conductive.
The flip chip bonding process has certain difficulties that adversely affect yield, reliability, and other device performance aspects. In the case of flip chip mounting of a vertical chip, potential exists for the solder to seep out of the gap between the chip and the sub-mount and contact a chip sidewall or the substrate, producing parasitic losses or, in extreme cases, failure of the device due to shorting. Such migration of the solder material can occur during placement of the chip, or during subsequent solder reflow. Indeed, some vertical chip manufacturers advise against flip chip bonding using soldering, and instead recommend other techniques such as thermocompressive or thermosonic bonding. These techniques are typically more complex than soldering, and may involve separate application of compressive or sonic energy to each individual chip.
In the case of lateral chips, soldering is also problematic. In addition to the potential for solder migration to the chip sidewalls, in a lateral chip the solder may also migrate into the area between the n- and p-electrodes located on the same side of the chip. Such migration again has the potential to produce parasitic or shorting paths. Again, resort is sometimes made to thermocompressive bonding, thermosonic bonding, or another non-solder based bonding technique.
Problems of solder migration are also affected by mechanical tolerances of the fabrication equipment or processes. Because relative misalignment of the solder and chip enhances the likelihood of forming parasitic or shorting solder pathways, it is advantageous to use solder application and chip placement machines having tight tolerances. This, however, increases fabrication costs, and additionally there are practical limits to the achievable tolerances. Requiring tight tolerances on solder application chip placement can also adversely affect yield by causing more devices to fail to meet specification.
Apart from the aforementioned problems, another difficulty with soldering is that it can produce a high chip profile in the fabricated device. The height of the chip is a combination of the chip thickness and the height of the solder bumps. Laser lift-off or other substrate removal or thinning techniques can reduce the chip profile, but only by the thickness of the substrate.